1. Field of the Invention
This disclosure relates to a semiconductor device, and more particularly, to a dynamic random access memory (DRAM) and a method of manufacturing the same.
2. Description of the Related Art
As techniques for manufacturing semiconductor devices develop and the applications for memory devices expand, memory devices having large capacities are required. In particular, the integration density of a DRAM device, wherein a memory cell is composed of one capacitor and one transistor, has remarkably improved.
As the integration density of semiconductor device increases, the size of contact hole connecting one element to another element or one layer to another layer decreases, but the thickness of an interlayer dielectric layer increases. Thus, the aspect ratio of the contact hole, i.e., the ratio between its height to its diameter, increases and an alignment margin of the contact hole decreases in a photolithography process. As a result, the formation of small contact holes by conventional methods becomes very difficult.
In DRAM devices, a technique for forming landing pads is widely used to reduce the aspect ratio of a contact hole, and a self-aligned contact (SAC) structure is applied to a pattern having a feature size of about 0.1 m or less to settle short-circuit problems caused by the decrease of an alignment margin of the contact hole.
FIGS. 1A and 1B are cross-sectional diagrams illustrating a conventional method of manufacturing a DRAM device having SAC pads.
Referring to FIG. 1A, a semiconductor substrate 10 is divided into active regions and isolation regions by an isolation process such as a trench isolation process. A thin gate oxide layer (not shown) is grown on the surfaces of the active regions by a thermal oxidation process. Gate electrodes 18 of metal oxide semiconductor (MOS) transistors serving as word lines are formed on the gate oxide layer. Preferably, each of the gate electrodes 18 is formed to have a polycide structure including a polysilicon layer 14 doped with an impurity at a high concentration and a tungsten silicide layer 16 formed on the polysilicon layer 14.
The gate electrode 18 includes a gate mask layer 20 formed on the tungsten layer 16 and a gate spacer 22 formed on a sidewall of the gate electrode 18. The gate mask layer 20 and the gate spacer 22 are formed using silicon nitride.
Source/drain regions (not shown) of the MOS transistors are formed in the surface portions of the substrate 10 exposed between the gate spacers 22. The source/drain regions are formed via an ion implantation process using the gate electrodes 18 and the gate spacers 22 as masks.
A first interlayer dielectric layer 24 is formed on the surface of the substrate 10 including the MOS transistors formed thereon. The first interlayer dielectric layer 24 is etched using bar-type mask patterns including openings that expose the active regions when the surfaces of the source/drain regions between the gate electrodes 18 are exposed.
A first conductive layer is formed on the first interlayer dielectric layer 24 using doped polysilicon to fill up the openings. The first conductive layer is planarized via a chemical mechanical polishing (CMP) process when the surfaces of the gate mask layers 20 are exposed. As a result, first and second contact pads 26a and 26b are formed in the openings. The first and second contact pads 26a and 26b make contact with the source/drain regions. In addition, the first and second contact pads 26a and 26b are self-aligned relative to the gate electrodes 18.
A second interlayer dielectric layer 28 composed of silicon oxide is formed on the first interlayer dielectric layer 24 and on the contact pads 26a and 26b. The second interlayer dielectric layer 28 is then planarized via a CMP process or an etch-back process. The second interlayer dielectric layer 28 is partially etched by a photolithography process so that bit line contact holes 30 exposing the second contact pads 26b are formed over the drain regions.
A second conductive layer and a silicon nitride layer are sequentially formed on the second interlayer dielectric layer 28 to fill up the bit line contact holes 30. The silicon nitride layer and the second conductive layer are patterned via a photolithography process so that bit lines 32 including bit line masks are formed on the second interlayer dielectric layer 28.
A third interlayer dielectric layer 36 is formed on the entire surface of a resultant structure using silicon oxide. The third interlayer dielectric layer 36 is then planarized via a CMP process or an etch-back process. The third interlayer dielectric layer 36 and the second interlayer dielectric layer 28 are partially etched by a photolithography process such that storage node contact holes 38 exposing the first contact pads 26a are formed over the source regions. Here, the storage node contact holes 38 are formed to have a line shape so that the first contact pads 26a adjacent to one another in a direction identical to the gate direction are simultaneously exposed.
Referring to FIG. 1B, a silicon nitride layer is formed in the storage node contact holes 38 and on the third interlayer dielectric layer 36. The silicon nitride layer is then anisotropically etched to form contact spacers 40 on the inner sidewalls of the storage node contact holes 38.
A third conductive layer composed of doped polysilicon is formed to fill the storage node contact holes 38 on the third interlayer dielectric layer 36. The third conductive layer is then planarized via a CMP process when the surface of the third interlayer dielectric layer 36 is exposed. Accordingly, storage node contact plugs (not shown) separated into node units are formed in the storage node contact holes 38, respectively.
According to the conventional method, the recesses of the silicon nitride gate mask layers 20 are formed during the etching process for forming the SAC pads 26a and 26b, and also during the CMP process for separating the contact pads 26a and 26b into node units. Furthermore, the recesses of the gate mask layers 20 are generated during the etching process for forming the contact spacers 40. Hence, the gate mask layers 20 do not sufficiently protect the underlying gate electrodes 18. When the thickness of the gate mask layer 20 is increased to resolve this problem, gate notching may occur due to a low etching selectivity between the photoresist film and the silicon nitride layer.
Since the initial width of the gate mask layer 20 is limited, the width of the gate mask layer 20 decreases continuously as the etching process for forming the SAC pads and subsequent processes are carried out, thereby exposing edge portions of the gate electrodes 18. As a result, the bit lines 32 may be electrically short-circuited with the gate electrodes 18 (refer to portion “C” in FIG. 1A) or the storage node contact plugs may be electrically short-circuited with the gate electrodes 18 (refer to portion “D” in FIG. 1B).